
ICS843002I-41
700MHZ, FEMTOCLOCK VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
11
ICS843002AKI-41 REV. B
APRIL 7, 2009
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The
ICS843002I-41 provides separate power supplies to isolate any
high switching noise from the outputs to the internal PLL. VCC,
VCCA, VCCO_LVPECL and VCCO_LVCMOS should be individually
connected to the power supply plane through vias, and 0.01F
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that
an additional 10
Ω resistor along with a 10μF bypass capacitor be
connected to the VCCA pin.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
VCC
VCCA
3.3V
10
Ω
10F
.01F
V_REF
Single Ended Clock Input
VCC
CLKx
nCLKx
R1
1K
C1
0.1u
R2
1K